PCB Trace Width Calculator

PCB Trace Width Calculator supports engineering calculations with transparent assumptions, practical result interpretation, and links to next-step technical resources.

Trace Geometry Visualizer

IPC-2221 Equation

I = k × ΔT^0.44 × A^0.725

A = (I / (k × ΔT^0.44))^(1 / 0.725)

W = A / t

k = 0.048 (external) or 0.024 (internal), A in mil², t and W in mil.

PCB Cross-Section

Width vs Current Curve

Enter current and temperature rise to render trace sizing curve.

Inputs & Outputs

Current (I)

Temperature Rise (ΔT)

°C

Copper Weight

Optional Voltage Drop Estimate

Trace Length

Ambient Temp (optional)

°C

Required Width—

Cross-Section Area—

Copper Thickness—

Current Density—

Length-Based Electrical Estimates

Enter trace length to compute resistance, voltage drop, and power loss.

PCB Trace Sizing Fundamentals

Required trace width depends on allowable temperature rise and copper cross-section. External traces cool more easily than internal traces, so required width differs even at the same current.

Current-Thermal Equation

I = k × ΔT^0.44 × A^0.725

A in mil², k differs by layer location.

Solve A first, then divide by copper thickness to get width.

Voltage Drop Awareness

R = ρ × L / A, Vdrop = I × R, Ploss = I² × R

Longer routes and narrow widths quickly raise drop and heating.

Use length estimate early for low-voltage rails.

Copper Weight Reference

Quick nominal thickness mapping from copper weight for early layout sizing decisions.

Copper Weight	Thickness (mil)	Thickness (mm)	Typical Use
0.5 oz/ft²	0.689 mil	0.0175 mm	Dense signal routing, low to medium current
1 oz/ft²	1.378 mil	0.0350 mm	General control and mixed-signal boards
2 oz/ft²	2.756 mil	0.0700 mm	Power distribution and motor driver stages
4 oz/ft²	5.512 mil	0.1400 mm	High-current bus routing, thermal robustness

Trace Design Selection Matrix

Align electrical and thermal goals with layer strategy and board manufacturability constraints.

Scenario	Objective	Recommendation	Critical Checks
External power trace routing	Balance board area and allowable thermal rise	Start with external-layer model and lower rise target for reliability margin.	Copper pour heat spreading, solder mask effect, airflow condition
Internal plane-fed branches	Route constrained traces in multilayer stackup	Use internal-layer coefficient and validate via post-layout thermal simulation.	Dielectric thermal path, via stitching, local hotspot under components
Low-voltage high-current rails	Limit voltage drop and copper loss	Use optional length-based resistance estimate and iterate copper weight vs width.	Drop budget, connector IR loss, transient current peaks